Computing devices, particularly portable devices, are frequently limited by the amount of time that they can run on battery power without reconnection to an AC power supply. Thus, there is a continuous effort to reduce the power consumption of various components of computers, including the central processing unit. Keeping electronic devices such as a central processing unit, a memory controller or a memory in their lowest possible power state provides a number of benefits. For example, it allows battery-operated machines to operate for longer periods of time between recharging. A reduction in power consumption also reduces thermal dissipation by the central processing unit. Reduced thermal dissipation allows the central processing unit to run at full speed for longer periods of time, while remaining within its thermal dissipation specifications. Reduced thermal dissipation also reduces the need for fans and other components used to prevent heat build-up in a computer.
A standard specification used in developing power management systems is the advanced configuration and power interface (ACPI) specification (for example, rev. 2.0 dated Jul. 27, 2000; see also ACPI Component Architecture Programmer Reference, rev. 1.05 dated Feb. 27, 2001 available from Intel Corporation of Santa Clara, Calif.). One goal of the ACPI is to enhance power management functionality and robustness, as well as facilitating industry wide implementation of common power management features.
The ACPI defines a number of processor power states that are processor power consumption and thermal management states within a global working state. These processor states include a (i) CØ power state, (ii) C1 power state, (iii) C2 power state, and (iv) C3 power state. In the CØ power state, the processor executes instructions and is at full power. In the C1 and C2 power states, the processor is in a non-executing power state. However, the C2 power state uses less power than the C1 state. In the C1 and C2 power state, the processor still allows the bus to snoop the processor cache memory and thereby maintain cache coherency. The C3 power state offers improved power savings over the C1 and C2 power states, but at the cost of higher power down exit latency to memory.
In conventional systems, the power management logic causes the CPU to transition from a C2 power state back to a high-powered CØ power state under certain circumstances. Keeping the electronic device in a lower power state than could otherwise be achieved and reducing the number of transitions between power states improves system performance by reducing latencies caused by switching between designated power states, as well keeping the overall power consumption lower.